1. Field of the Invention
The present invention relates generally to data processing computer systems and, more particularly, to the transfer of data between a host processor and at least one I/O device.
2. Description of the Prior Art
A typical computer-based processor system (or computer system) consists of three major subsystems: a main memory, one or more host processors (the term CPU, host processor, and processor will be used interchangeably in this disclosure), and an input-output (I/O) subsystem. In order to provide communication between the host processor and a plurality of external input/output (I/O) devices, such as disks, tapes, printers, display devices, it is effective for data processing systems to utilize an intermediate control unit, also known as an I/O controller.
The I/O controller facilitates interchange of data between a computer system and remote peripheral devices. As a result, I/O controllers relieve the main host processor of many of its operating cycle obligations for ensuring that data exchanges between various remote peripheral devices and the main host processor system is accomplished with minimal interruption to the main host processor.
In most conventional systems utilizing such an approach, the host processor supplies an appropriate command to the I/O controller. The I/O controller then interprets the commands so that the selected I/O device can be identified and the appropriate data processing and transfer operations can occur. The host normally supplies such commands in sequence and the I/O processor processes such commands in such sequence. If the I/O processor is busy with a particular command requiring the servicing of a specified I/O device, then the host must wait until that process is complete before it can issue subsequent commands related to either the same or a different I/O device.
Conventional microprocessor systems usually consist of a single transmission medium, known as a bus, having an array of common conductors onto which many circuit elements are coupled. In a typical system, all the I/O devices and the memory devices must share the same processor bus 150 as shown in FIG. 1. Clearly, only one device in the system can transmit data onto the common bus at any given time, further slowing the transfer of data between peripheral devices and the host processor.
A more detailed description of some of the basic concepts discussed in this section is found in a number of references, including John L. Hennessy et al., Computer Architecture--A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., 1990); and the i486.TM. Microprocessor Programmer's Reference Manual and the i486.TM. Microprocessor Hardware Reference Manual (Order Nos. 240486 and 240552, respectively, Intel Corporation, Santa Clara, Calif., 1990). These documents are incorporated by reference herein in their entirety.